The invention relates to a method of improving integrated circuit semiconductor yields and, more specifically to a method of minimizing pipes which result in shorts or leakages between two conductivity types of the semiconductor devices.
The present aim in semiconductor integrated circuit technology is to achieve higher and higher levels of integration by exceeding a density of about several thousand circuits per square millimeter on a semiconductor wafer. Because of this high packing density, the presence of microdefects such as precipitates, migration of impurities, in addition to crystallographic defects like dislocations, stacking faults, having a dominating influence on yield, performance and reliability of the semiconductor devices. These defects generally cause pipes in the bulk silicon material resulting in shorts between emitter and collector, lower breakdowns, soft junctions, non-uniform doping, and many changes of the carrier lifetime, of resistivity, etc. which in turn result in modifications of some of the important device parameters such as gain, leakage currents, saturation voltage, etc. with undesired secondary consequences regarding power dissipation, noise generation, etc.
The pipe phenomenon is well known in the semiconductor art. There are a number of types, one of which results from the surface microdefects in the silicon wafer substrate on which is formed the epitaxial layer. These are upwardly extending pipes or dislocation lines. Another type of pipe results from microdefects in the surface and body of the epitaxial layer. These are downwardly extending pipes or dislocation lines and are the type to be addressed by the present invention. For example, pipes in NPN transistors appear as N-type regions extending from the N emitter region to reach the N collector region through the P-type base region. More specifically, crystallographic defects such as stacking faults and dislocations often act as sites for pipe information. Enhanced diffusion often takes place along these defects particularly along dislocation lines. This results in emitter-collector shorts or leakages which as previously stated, are detrimental to good device performances.